Hardware/software design requirements planning - Part 2: Decomposition using structured analysis
Jeffrey O. Grady, JOG Systems Engineering, Inc.
EETimes (11/7/2011 11:41 PM EST)
In this series of articles, Jeffrey O. Grady, author of “System Verification,” delineates the basics of requirements planning and analysis, an important tool for using Agile programming techniques to achieve better code quality and reliability in complex embedded systems software and hardware projects. Part 2: Decomposition using structure analysis Structured decomposition is a technique for decomposing large complex problems into a series of smaller related problems. We seek to do this for the reasons discussed earlier.
We are interested in an organized or systematic approach for doing this because we wish to make sure we solve the right problem and solve it completely. We wish to avoid, late in the development effort, finding that we failed to account for part of the problem that forces us to spend additional time and money to correct and brings into question the validity of our current solution.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- Routing density analysis of ASICs, Structured ASICs, and FPGAs
- Hardware/software design requirements analysis: Part 1 - Laying the ground work
- Hardware/software design requirements planning: Part 3 - Performance requirements analysis
- System Performance Analysis and Software Optimization Using a TLM Virtual Platform
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow