GenAI-Driven Approach to RISC-V Supply Chain Exploration
By Nenad Petrovic, Andre Schamschurko, Yingjie Xu, and Alois Knoll
Chair of Robotics, Artificial Intelligence and Real-Time Systems
Technical University of Munich, Germany

Abstract
This paper presents an LLM-empowered workflow for RISC-V supply chain analysis, integrating Vision-Language Models (VLMs) and Model-Driven Engineering (MDE) to enable comprehensive, multimodal data-driven insights. The proposed approach addresses the challenges of heterogeneous and unstructured supply chain data by leveraging LLMs for textual understanding and VLMs for extracting information from visual artifacts such as diagrams, tables, and scanned documents. These models collaboratively identify key entities and relationships, which are then organized into a knowledge graph representing supply chain components and their interdependencies. For analytical reasoning, the workflow incorporates MDE techniques and constraint-based modeling to enable formal validation of dependencies, detection of bottlenecks, and assessment of risks. The synergy between LLM- and VLM-based semantic understanding and MDE-based formal analysis supports both exploratory and systematic evaluation of supply chain resilience. A human-in-the-loop mechanism further enables interactive querying and expert validation. The approach is evaluated in RISC-V ecosystem scenarios, demonstrating its effectiveness in generating actionable insights, enhancing transparency, and supporting decision-making in complex semiconductor supply chains.
Keywords: Automotive,Cybersecurity, Functional Safety, Event Chain, Large Language Models (LLMs), SDV
To read the full article, click here
Related Semiconductor IP
- RISC-V Display Connectivity Subsystem (DCS)
- RISC-V IOPMP IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
Related Articles
- Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs
- An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2
- ASICs Bring Back Control to Supply Chains
- Reverse Disaggregation - How Silicon IP Will Change the Semiconductor Supply Chain
Latest Articles
- GenAI-Driven Approach to RISC-V Supply Chain Exploration
- HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
- Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM
- Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
- TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing