Implementing high Speed USB functionality with FPGA- and ASIC-based designs
Hridya Valsaraju and Gopalakrishnan Vijayakumar, Cypress Semiconductors
EETimes (10/18/2011 5:26 PM EDT)
The Universal Serial Bus (USB) has earned the popularity it now enjoys based on the merits of its ease of use, plug-and-play capabilities, and robustness. USB has, more or less, found its way into all the computer peripherals that once contained UARTs or parallel ports as their host interfaces, and any product which requires an interface to a host computer now considers USB as its primary option.
The various bandwidth choices that the USB offers – Low, Full, High, and now Super speed – cater to a variety of computer peripherals as well as industrial and medical equipment.
The throughput offered by USB is sufficient even for high bandwidth applications like hard disk drives and scanners. Indeed, for most of the computer peripherals like keyboards and mice, PDAs, gamepads, joysticks, scanners, digital cameras and printers, USB is now the standard interconnection method.
To read the full article, click here
Related Semiconductor IP
- USB TYPE-C Verification IP
- USB PD Verification IP
- USB 4.0 Verification IP
- USB 3.0/3.1/3.2/SSIC Verification IP
- USB 1.0/1.1/2.0 Verification IP
Related Articles
- FPGA debugging techniques to speed up pre-silicon validation
- Generating High Speed CSI2 Video by an FPGA
- Reconfiguring Design -> FPGAs speed audio application development
- SoC Test and Verification -> Assertions speed processor core verification
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow