Embedded system virtualization for executable specifications and use case modeling
By Vincent Perrier, CoFluent Design (Nantes, France)
edadesignline.com (January 26, 2010)
Specifying and validating embedded systems and chips becomes increasingly challenging as feature sets and non-functional constraints grow. It's especially difficult when the system involves a multicore programmable platform, which includes several processing engines such as microprocessors, microcontrollers or DSPs, that run application software distributed across the various cores.
The development of the hardware (HW) platform — system-on-chip (SoC) or board — and the application software (SW) is usually done by separate teams, and often by separate companies. In general, the hardware platform development team includes software engineers in charge of developing low-level platform-dependent software — also called firmware (FW) — including boot loaders, C runtime and libraries, operating systems and device drivers. Software engineers also usually develop middleware (MW), including protocol stacks and various libraries, providing specific application programming interfaces (API) to application software developers — the platform users.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- Enabling error resilience throughout the embedded system
- Selecting an operating system for an embedded application
- Secure Virtualization as an Enabler of Trusted Execution Environments in Embedded Computing
- Enabling security in embedded system using M.2 SSD
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST