Designing with an embedded soft-core processor
By Don Arbinger and Jeremy Erdmann, The Plexus Technology Group
Mar 29 2006 (12:00 PM), Embedded.com
When designing an embedded solution, the designer will have product level requirements that mandate the processing of various inputs to yield predictable outputs.
There will be a number of acceptable options to choose from when selecting the type of design that will be used for the controller. The first solution is a “Discrete” microprocessor, which seem to be the most commonly used solution. The second solution is a “hard” processor core, which will be embedded in hardware as dedicated silicon in either an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).
<>Alternatively, an embedded soft-core processor may be a viable solution where the processor is implemented in the primitives of an FPGA. The decision regarding the type of controller used is typically based on a balance between schedule, unit cost, space constraints, product lifetime, toolset, and flexibility needs.
Different options are available to a designer needing to select a microprocessor. Some options provide more benefits over others; however, not all options are a fit for every application. The key is to know what is needed for the application and then select the correct option that will suit the application. Three processing options will be briefly discussed here: the “discrete” OTS (Off the shelf) processor, a hard processor core, and finally the soft processor core.
Mar 29 2006 (12:00 PM), Embedded.com
When designing an embedded solution, the designer will have product level requirements that mandate the processing of various inputs to yield predictable outputs.
There will be a number of acceptable options to choose from when selecting the type of design that will be used for the controller. The first solution is a “Discrete” microprocessor, which seem to be the most commonly used solution. The second solution is a “hard” processor core, which will be embedded in hardware as dedicated silicon in either an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).
<>Alternatively, an embedded soft-core processor may be a viable solution where the processor is implemented in the primitives of an FPGA. The decision regarding the type of controller used is typically based on a balance between schedule, unit cost, space constraints, product lifetime, toolset, and flexibility needs.
Different options are available to a designer needing to select a microprocessor. Some options provide more benefits over others; however, not all options are a fit for every application. The key is to know what is needed for the application and then select the correct option that will suit the application. Three processing options will be briefly discussed here: the “discrete” OTS (Off the shelf) processor, a hard processor core, and finally the soft processor core.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Software Infrastructure of an embedded Video Processor Core for Multimedia Solutions
- Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- Embedded Software Unit Testing with Ceedling
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety