Demystifying ESL for embedded systems designs
By Shelley Gretlein, National Instruments
Mar 1 2007 (1:00 AM) -- Embedded Systems Design
While the definitions of ESL may vary, the end result should be the same, namely letting system developers analyze their designs at a higher level of abstraction.
A recent Google search on "electronic system level" yielded more than 86,900 results (and growing daily), quickly demonstrating how much information is available on this topic. But despite the abundance of buzz, it's not always easy to find a clearcut explanation of what this design method encompasses and how it applies to embedded systems design. From the broadest perspective, electronic system level (ESL) design consists of tools and methods that enable designers to describe and analyze ICs at a high level of abstraction.
This original definition was targeted at high-end chip designers. If you look at a concept introduced by Wired's Editor in Chief Chris Anderson called "the long tail," these high-end applications fit into the "head" as more high-volume and vertical applications.1 This concept is visualized in Figure 1.
Mar 1 2007 (1:00 AM) -- Embedded Systems Design
While the definitions of ESL may vary, the end result should be the same, namely letting system developers analyze their designs at a higher level of abstraction.
A recent Google search on "electronic system level" yielded more than 86,900 results (and growing daily), quickly demonstrating how much information is available on this topic. But despite the abundance of buzz, it's not always easy to find a clearcut explanation of what this design method encompasses and how it applies to embedded systems design. From the broadest perspective, electronic system level (ESL) design consists of tools and methods that enable designers to describe and analyze ICs at a high level of abstraction.
This original definition was targeted at high-end chip designers. If you look at a concept introduced by Wired's Editor in Chief Chris Anderson called "the long tail," these high-end applications fit into the "head" as more high-volume and vertical applications.1 This concept is visualized in Figure 1.
To read the full article, click here
Related Semiconductor IP
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
Related Articles
- ACE: Confidential Computing for Embedded RISC-V Systems
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Android, Linux and Real-Time Development for Embedded Systems
- NAND Flash memory in embedded systems
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing