Complex SoC Testing with a Core-Based DFT Strategy

By Sandeep Kaushik, Synopsys and Paul Policke, Qualcomm
(02/26/08, 10:08:00 AM EST) -- EDA DesignLine

With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically - making it almost impossible to test an entire design once it reaches manufacturing. But, using a core-based test strategy combined with scan compression offers one of the most effective ways to limit both huge data volumes and high power consumption of complex SoC tests.

Traditional scan-based test techniques are losing ground against today's SoC designs. The growth in chip size and the number of scan flip-flops equates to an overwhelming increase in the number of automatic test pattern generation (ATPG) patterns and the number of shift cycles per ATPG pattern. Adding delay testing to the scan architecture further increases the number of ATPG patterns, which puts further demands on automatic test equipment (ATE) memory.

Power consumption during test has also been increasing due to the tremendous switching activity of ATPG patterns and leaky processes. High dynamic power during scan shifting and capture can burn the device, while high instantaneous power can lead to excessive IR drop and ultimately device failure.

Using a core-based divide-and-conquer approach helps to overcome the challenges of high power consumption and huge data volume generated during testing. This article describes the results achieved by Qualcomm, with the help of Synopsys Professional Services, using multi-mode test architecture on its 65nm DSP core; DFT MAX was used for scan compression, and DFT Compiler was used for core-isolation implementation.

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