Building eye-catching GUIs for your embedded MCU designs
Francis Lamotte, KEOLABS
embedded.com (December 18, 2013)
This article describes how integration of 2D Direct Memory Access (DMA2D) in microcontrollers creates new possibilities for graphics use in user interfaces by placing limits on device and application coding costs, at the same time improving core processor performance. It describes the key features of DMA2D and how developers can implement these features in application software, with code examples that engineers can use in their own applications. The examples cover techniques for:
- Handling of bitmaps (display, overlaying and moving)
- Using transparency (pixel-level, global and blending)
- Dynamic versus Read-Only objects
- Management of objects and touch sensing
- Use of layering (Z-order)
- Transformations of graphic objects
- Use of memory spaces including external SDRAM resources.
Chrome-ART acceleration for MCU GUI applications
Thanks to the ease of implementing touch sensing and the improved price points for displays and 32-bit MCUs, graphical user interfaces (GUI) have become increasingly present in MCU applications. Because they are attractive, flexible, and interactive, GUIs are an excellent way to enhance both application functionality and the user’s experience.
In spite of this evolution, some technical challenges have persisted. Typical GUI implementations on microcontrollers (unlike high-end processors targeting mobile appliances) have been limited by how much of their processing power, peripherals, and memory resources could be allocated to managing the display and graphics.
Relatively limited memory, processing power, and resulting code complexity all conspired to make implementation costly and responsiveness of the GUI relatively limited.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Building a Total Quality Experience into Silicon IP - Delivering DesignWare Silicon IP into SoC Designs
- How to choose an RTOS for your FPGA and ASIC designs
- How to defend against the cloning of your FPGA designs
- How to achieve quality assurance for your electronic designs
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace