Bringing SOT-MRAM Tech Closer to Cache Memory
By Farrukh Yasin, Van Dai Nguyen, Siddharth Rao and Gouri Sankar Kar (imec)
EETimes (December 12, 2024)
For many decades, ultrafast and volatile SRAM has been used as embedded cache memory in high-performance compute architectures, where it resides very close to the processor in a multi-level (L1, L2, L3) hierarchical system. Its role is to store frequently used data and instructions for quick retrieval, with L1 being the fastest of all cache memories. SRAM bit density scaling has been slowing down for some time, and bit cells increasingly suffer from standby power issues.
The spin-orbit torque (SOT)-MRAM memory solution has several advantages, such as low standby power consumption, GHz-level switching or write speeds, negligible leakage, practically unlimited endurance, high reliability, and scalability. For these reasons, the industry is increasingly evaluating SOT-MRAM as a promising alternative to SRAM in embedded last-level, cache-memory applications.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- How to accelerate memory bandwidth by 50% with ZeroPoint technology
- Multi Chip, Multi Environment Simulation, Bringing Software Closer to Hardware and Saving Money
- Using scheduled cache modeling to reduce memory latencies in multicore DSP designs
- Which DDR SDRAM Memory to Use and When
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices