Bringing SOT-MRAM Tech Closer to Cache Memory

By Farrukh Yasin, Van Dai Nguyen, Siddharth Rao and Gouri Sankar Kar  (imec)
EETimes (December 12, 2024)

For many decades, ultrafast and volatile SRAM has been used as embedded cache memory in high-performance compute architectures, where it resides very close to the processor in a multi-level (L1, L2, L3) hierarchical system. Its role is to store frequently used data and instructions for quick retrieval, with L1 being the fastest of all cache memories. SRAM bit density scaling has been slowing down for some time, and bit cells increasingly suffer from standby power issues.

The spin-orbit torque (SOT)-MRAM memory solution has several advantages, such as low standby power consumption, GHz-level switching or write speeds, negligible leakage, practically unlimited endurance, high reliability, and scalability. For these reasons, the industry is increasingly evaluating SOT-MRAM as a promising alternative to SRAM in embedded last-level, cache-memory applications.

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