Considerations Regarding Benchmarking eFPGAs (Embedded FPGAs)
By Tony Kozaczuk, Flex Logix Technologies
May 18, 2018
There are many things to consider, but if you choose the right solution for your particular application, you will be able to unlock the full potential of your eFPGA.
Embedded FPGA, or eFPGA, refers to one or more blocks of FPGA fabric that are embedded in a device like an ASIC, ASSP, or SoC.
To put this another way, eFPGA is a digital reconfigurable fabric consisting of programmable logic in a programmable interconnect, normally presented as a rectangular array, with data inputs and outputs positioned around the edges. An eFPGA typically has hundreds or thousands of inputs and outputs that can be connected to busses, data paths, control paths, to GPIOs or PHYs or whatever is desired.
All eFPGAs have look-up tables (LUTs) as basic building blocks. A LUT has N inputs selecting a small table whose outputs then represent any desired Boolean function of the N inputs. Some eFPGA LUTs have four inputs and some have six. Some LUTs have two outputs. LUTs typically have flip-flops on the outputs; these can be used to store the result or they can be bypassed. These LUT-register combos typically come in groups of fours, along with carry arithmetic and shifters to enable the efficient implementation of adders.
To read the full article, click here
Related Semiconductor IP
- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
- Radiation-Hardened eFPGA
- eFPGA Hard IP Generator
- eFPGA Soft IP
- eFPGA on GlobalFoundries GF12LPP
Related Articles
- Choosing the best Standard Cell Library without falling into the traps of traditional benchmarking methods
- eFPGA Creator GUI Tools Suite: A complete hardware and software infrastructure for creating customizable eFPGA IP blocks of Menta
- eFPGA IP Density, Portability & Scalability
- The Ideal Solution for AI Applications - Speedcore eFPGA
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices