How to select an AES solution
pldesignline.com -- July 16, 2008
The Advanced Encryption Standard (AES) replaced DES and Triple DES in 2001 as the preferred symmetrical cryptographic cipher for the 21st Century. The US government's National Institute of Science and Technology (NIST) mandated AES for civilian agencies and the National Security Agency (NSA) has authorized AES for encryption of classified information.
AES is an open standard (see fips-197.pdf) that was selected from an open competition. The winner was the Rijndael algorithm because it combines an extremely high level of security with computational efficiency. The algorithm consists of Exclusive-OR functions combined with matrix operations and is a mathematically 'clean' design which avoids the risk of 'back doors' to unauthorized users.
The elegance and efficiency of the system makes it suitable for either hardware or software systems. Low data rates can be accomplished by software only solutions. Hardware solutions are, of course, much faster and are often specified because implementing the critical security components in hardware isolates them from software threats such as 'viruses'. This avoids the need to carry out a detailed and costly security analysis of all the software components in the system.
To achieve higher data throughput designers can use a SoC (ASIC) or FPGA platform to provide hardware acceleration. This is where another feature of AES comes into play, the scalability of the algorithm. Fig 1 gives a typical trade-off between throughput and equivalent ASIC gate count and exhibits a nearly linear relationship between complexity and data rate.
To read the full article, click here
Related Semiconductor IP
- AES
- AES
- AES-SX-ULP-full Secure Core - High-Performance, Ultra Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection
- AES-SX-ULP-full Secure Core - High-Performance/Ultra Low Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection
- AES-SX-ULP-full Secure Core - Ultra-Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection
Related Articles
- Customized FPGA board for ASIC Prototyping - A novel approach with Predesigned Blocks and Modular FPGA
- What’s the number of ASIC versus FPGA design starts?
- General Partitioning Guidelines for Validation of Large ASIC Designs On FPGA
- Resets in FPGA & ASIC control and data paths
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing