What's Really Behind the Adoption of eFPGA?
By Andy Jaros, VP of Flex Logix
System companies are taking a more proactive role in codesigning their hardware and software roadmaps, so it’s no surprise that they are also driving the adoption of embedded FPGAs (eFPGA.)
But why and why has it taken so long?
Today, most system companies leverage FPGAs to offload intensive compute workloads from the main processor or provide broader IO capability than any packaged ASIC can support. In these examples, the FPGA is used to connect any hard wired accelerator to the ASIC processor subsystem or facilitates the connection between the ASIC and the system’s bus. By definition, the FPGA is universal as it is a blank programmable fabric regardless if it’s from Intel, Xilinx, Lattice, etc., which makes it invaluable to system companies who can’t get the functionality they really need or want from their semiconductor partner. Plus, they get the added benefit that they don’t have to share their proprietary circuitry with their semiconductor partner or other companies in the supply chain.
To read the full article, click here
Related Semiconductor IP
- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
- Radiation-Hardened eFPGA
- eFPGA Hard IP Generator
- eFPGA Soft IP
- eFPGA on GlobalFoundries GF12LPP
Related Articles
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- Customized DSP -> DSP IP cores fuel PLD adoption
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing