Adapting signal integrity to nanometer IC design

Vinod Kariat and Rahul Deokar, Cadence Design Systems
(04/10/2006 9:00 AM EDT), EE Times
 
Although the term signal integrity, or SI, is very common in the EDA industry, it has come to mean different things to different people.

In its truest sense, signal integrity is helps ensure that a signal can faithfully propagate to its intended destination with the right logic value within an allocated time. Over the last few years, as we have seen designs move from 130 nanometers to 90 nanometers to 65 nanometers, the complexity of the SI challenge has created a need for three distinct SI analysis disciplines: IR drop analysis, functional noise analysis, and analysis of the effect of noise on timing.

As SI capabilities have become incorporated into mainstream analysis and implementation tools, it is easy to be lulled into believing that SI is a solved problem. However, this is not the case.

Significant improvements must be made to existing SI analysis techniques to reduce false errors. In addition, the new emphasis on low power design and the migration to 45 nanometers creates even more new issues in SI analysis that must be addressed. In the long term, we will need to look at SI analysis very differently than we do today.

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