A consumer reports methodology for IP
Piyush Sancheti, Atrenta
EETimes (5/7/2013 10:54 AM EDT)
As an SoC designer, you’re probably frustrated by how IP (3rd party and internal) can hinder your design getting to tapeout. After all, IP is supposed to be the cure-all for increasingly-complex SoC designs, right? However, it’s turned into a sometimes endless, difficult series of IP fixes. Why?
The answer is simple – it’s all about quality. Let’s think about this: the quality of today’s IP varies widely. SoC designers never know whether they will be able to use an IP block in multiple designs or if they will have a problem designing an IP block into just one design. SoC designers need better IP quality! They need a system to check the overall quality of the delivered IP, similar to a Consumer Reports analysis. And this analysis should enforce a quality standard so that the consumer has confidence that an IP block won't require difficult and time-consuming tweaks and fixes to work in the target design.
To ensure IP quality, design projects need to create such a Consumer Reports methodology. How do we get there? Here are some suggestions.
To read the full article, click here
Related Semiconductor IP
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
Related Articles
- Formal-based methodology cuts digital design IP verification time
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- SignatureIP's iNoCulator Tool - a Simple-to-use tool for Complex SoCs
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing