Truechip announces first customer shipment of LPDDR3 and LPDDR4 Comprehensive Verification IPs
February 17, 2015 - Truechip Solutions, the verification IP specialist, announced that it has shipped early adopter version of its LPDDR3 and LPDDR4 Comprehensive Verification IPs (CVIPs) to its partners in the early adoption program.
This CVIP is natively developed in SystemVerilog (UVM) and is architected such that a single VIP is able to provide comprehensive, seamless - Block, SoC and System Level, verification across dynamic simulation, assertion based dynamic and formal verification, as well as support for hardware acceleration and emulation. The CVIPs are compatible with all industry leading software and hardware platforms.
Nitin Kishore, CEO of Truechip, said in a statement, "LPDDR3 and LPDDR4 CVIP release is our third major product release of 2015 and fourth since December of last year. LPDDR CVIPs are a natural extension of our DDR CVIPs, and will further strengthen our position as an independent verification partner of choice for customers.”
To try out any of Truechip's high quality VIPs or experience industry's first 24X5 support, please visit www.truechip.net.
Truechip is also a member of MIPI Alliance. MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem and are committed to defining and promoting interface specifications for mobile devices.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- Truechip: Exhibiting and Showcasing Latest Verification IPs and NOC IPs at Design Automation Conference (DAC) 2023
- Truechip announces first customer shipment of DDR3 and DDR4 Verification IPs
- Truechip to demonstrate next generation Comprehensive Verification IPs at DAC 2015
- Truechip Announces Customer Shipment Of USB4 And eUSB Verification IPs
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers