TES introduces a low power 32kHz Pierce Oscillator IP for Battery-Powered ASICs and SoCs
September 28, 2026 -- TES Electronic Solutions GmbH announces the availability of TS_XOSC_32k_X8, a low-power 32.768 kHz Pierce crystal oscillator IP designed to provide a reliable low-frequency timing reference for battery-powered ASICs and system-on-chip (SoC) applications.
Designed for operation directly from a 2.5 V to 5.5 V VBAT supply, the TS_XOSC_32k_X8 combines extremely low power consumption with robust crystal-startup capability. The IP is implemented in X-FAB XC018 - 0.18µm CMOS technology and already silicon-proven.
The IP can be found here:
Low Power 32kHz Pierce Oscillator
Key features
- Ultra-low power consumption: 489 nA max average current
- Wide supply voltage: 2.5 V to 5.5 V
Applications
- Battery-powered ASICs and SoCs
- Low-power wearable and portable electronics
- Always-on and low-power clock domains
Explore TES Electronic IP:
Related Semiconductor IP
- Low Power 32kHz Pierce Oscillator
- XTAL oscillator in TSMC 7nm
- Low power XTAL oscillator, 4M~40MHz on SMIC 40nm
- Xtal Oscillator on TSMC CLN7FF
- Low Power 32KHz Crystal Oscillator on TSMC CLN16FFC
Related News
- TES Unveils High-Performance 8/40MHz Oscillator and Clock Buffer IPs for Reliable On-Chip Timing Solutions for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- TES unveils a next-generation Elliptic Curve Digital Signature Algorithm (ECDSA) IP Core for Secure IoT, Blockchain, and Industrial Systems
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- TES is extending its PMU IP portfolio for X-FAB’s XT018 - 0.18µm BCD-on-SOI technology.
Latest News
- TES introduces a low power 32kHz Pierce Oscillator IP for Battery-Powered ASICs and SoCs
- Racyics UCIe PHY IP for GlobalFoundries 22FDX reaches silicon
- Sofics Extends Interface Voltage Options in TSMC FinFET and Nanosheet Technologies
- aiMotive and Cadence Demonstrate Layer-by-Layer Workload Placement Across Independent AI Engines
- Alchip collaborates with Synopsys to Address Scale Up and Out Bandwidth Constraints