Tenstorrent releases RiescueD, a powerful framework for writing direct tests in RISC-V assembly
September 2, 2025 -- Over the coming months, Tenstorrent plans to open source a suite of tools under the RiESCUE umbrella, which provides a suite of python scripts and libraries for generating RISC-V tests.
Tenstorrent would first like to announce the release of RiescueD, the RiESCUE Directed Test Framework. This is a powerful framework for writing directed tests in RISC-V assembly and provides library for test generator development, with features including:
- Randomization: Random data and address generation
- Memory Management: Automatic page table generation and memory mapping
- Environment Simulation: Support for various privilege modes, paging modes, and virtualization
- OS Code Simulation: Pseudo OS for scheduling and exception handling

RiescueD works well with several popular RISC-V simulators:
- Spike: RISC-V ISA simulator
- Whisper: Tenstorrent’s RISC-V Simulator
- QEMU: Full system emulation (coming soon)
Learn more about getting started with installation and setup, check out the RiescueD User Guide, or visit our GitHub repository for source code, examples, and more information.
Related Semiconductor IP
- RISC-V CPU IP
- Tensix Cores for specialized acceleration
- 64-Bit 8-stage superscalar RISC-V processor
- Multi-core capable RISC-V processor with vector extensions
- 32 Bit - Embedded RISC-V Processor Core
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