Intelop announces a new Development platform based on Xilinx V5 FPGA for their TCP-Offload Engine SoC IP for customers to easily develop networking applications

This second generation Customizable Full TCP offload Engine also integrates GEMAC, ARP module, PLB/AMBA 2.0 bus interfaces with optional PCIe interfaces running at 2-Gbps. It is capable of implementing/ accelerating hundreds of simultaneous TCP sessions, delivering 10-20 X performance improvement over TCP/IP software implementations.

Santa Clara, California -- Feb 01, 2010 

--  Intelop Corporation, a leading high-end IP developer, customization & electronic engineering design services provider, today announced introduction of a new Xilinx V5 FPGA based development platform for their TCP offload engine SoC IP. The development platform FPGA integrates Full Offload TOE, ARP hardware module, G Bit Ethernet MAC and PLB bus interface and other system peripherals. It is targeted towards hundreds of layer 3, 4, 5 networking applications which run TCP/IP on various networks throughout the globe, many of these may need acceleration.  It is the only TOE engine that allows customers to customize TCP/IP related differentiated features and integrates so many other functions in hardware. All of TCP-connection related tasks, TCP-Payload transfer tasks, TCP-disconnection, TCP-session management overhead which traditionally is performed by TCP/IP software is accomplished by the hardware engines in TOE resulting in an order magnitude performance improvement. It is a new paradigm and new level of integration in networking hardware acceleration.  

Because of its advanced scalable architecture, it can be customized to implement differentiated features and performance requirements to meet customer’s specifications e.g. misc. protocol processing and monitoring at G-bit line rate, in addition to TCP/IP, ARP module, number of simultaneous connections, TCP/IP performance tuning based upon type of network/traffic and application usage, scalable packet FIFO size, scalable size of Session Management table, Session Parameters, scalable size of direct store Packet memories, integrated DDRn/SSRAM controllers (optional), choice of PHY interface - GMII or Serial and more.

This Integrated TOE SoC silicon IP with customizable features provides enhanced functionality in all networking equipment including; Layer-2-5 Switches/Routers, IPS/IDS appliances and Network Security appliances, Severs and high end NICs.  Advanced architecture with built in scalability allows customers to target it to many silicon libraries from FPGAs to  0.18 um-0.090 nm ASIC or SOC without compromising performance or functionality.

 “We utilized our expertise in designing highly successful and advanced technology Multi-Giga bit Networking equipment, Enterprise-class IDS/IPS, Network Security appliances employing SOCs also designed by intelop in defining the architecture of this TOE engine,” said K Masood. “We are excited about this new crown jewel and the ability to develop value-added network acceleration IPs and total solutions for our customers.” said Kevin Moore of Intelop.

Intelop Corporation is a custom IP developer, SoC/ASIC/FPGA integrator and engineering services provider for Networking, Network Security, Network/storage and Embedded Systems. They offer silicon proven semiconductor IP and services with comprehensive hardware and software experience.