Synopsys was not invited to join SystemVerilog OVM initiative
Peter Clarke, EE Times
(08/17/2007 6:43 AM EDT)
LONDON — Synopsys Inc., a leading supplier of EDA tools, intellectual property, and design services, was not invited to join the Open Verification Methodology (OVM) initiative recently announced by Cadence Design Systems Inc. and Mentor Graphics Corp.
Cadence (San Jose, Calif.) and Mentor (Wilsonville, Ore.) announced they had joined forces to promote a common approach to the verification of design files based on the SystemVerilog language on Thursday (Aug. 16). They called have called it the 'Open Verification Methodology' or OVM to emphasize that it is an open-source and freely available approach. Executives from the companies claimed that two-thirds of the verification market would support the approach.
(08/17/2007 6:43 AM EDT)
LONDON — Synopsys Inc., a leading supplier of EDA tools, intellectual property, and design services, was not invited to join the Open Verification Methodology (OVM) initiative recently announced by Cadence Design Systems Inc. and Mentor Graphics Corp.
Cadence (San Jose, Calif.) and Mentor (Wilsonville, Ore.) announced they had joined forces to promote a common approach to the verification of design files based on the SystemVerilog language on Thursday (Aug. 16). They called have called it the 'Open Verification Methodology' or OVM to emphasize that it is an open-source and freely available approach. Executives from the companies claimed that two-thirds of the verification market would support the approach.
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