STMicroelectronics restructures for the AI age
By Nick Flaherty, eeNews Europe (June 28, 2024)
ST aims to introduce new business structures and manufacturing and test strategies along with IP and chip designs in three quarters rather than two to three years using AI and digital twins.
“We have a lot of IP and traditionally the way we created IP was 80% in silicon and 20% for the rest but that created a monster that was difficult to qualify,” said Fabio Gualandris, president of manufacturing, quality and technology at ST Microelectronics at the Leti Innovation Days this week in Grenoble, France.
To read the full article, click here
Related Semiconductor IP
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
Related News
- Synopsys IC Compiler Enables Fully Automated 65-Nanometer Implementation Flow For ARM Cortex-A8 Processor
- Calypto Delivers Fully Automated Sequential Optimization Flow for High-performance IP Blocks
- Zeevo Announces Full Bluetooth Qualification for TC2000 System-On-A-Chip Platform
- Tality Achieves Latest Qualification for Bluetooth 1.1
Latest News
- RAAAM Selects Avnet ASIC as its VCA Partner for TSMC’s 2nm GCRAM Development and Qualification
- IBM Debuts World’s First Sub-1 Nanometer Chip Technology
- Panmnesia Unveils Next-Stage CXL Switch and Controller at ISCA 2026
- Akeana Collaborates with Samsung Electronics, fast-tracking RISC-V Customers, Ecosystem for Server and Agentic AI Silicon
- Arteris Technology Licensed by SiEngine for Next – Generation Automotive SoCs