Sofics Extends Interface Voltage Options in TSMC FinFET and Nanosheet Technologies

Specialty I/O topologies, co-designed with robust on-chip ESD protection, give SoC and chiplet designers expanded interface voltage, and I²C options on advanced processes

Aalter, BELGIUM –September 24, 2026 – Sofics BV, a leading provider of specialty I/O and electrostatic discharge (ESD) protection IP, today announced the availability of its specialty I/O topologies on TSMC’s advanced FinFET and Nanosheet technologies. Developed to address specialized customer requirements beyond the scope of standard – GPIO libraries, Sofics’ topologies enable higher interface voltages, such as 1.8V or 3.3V, with macros developed on TSMC’s leading-edge FinFET and Nanosheet-based process technologies.

As designers build AI, high-performance computing (HPC), chiplet, and automotive SoCs on advanced process nodes, these devices must frequently communicate with sensors, legacy components, and system-level interfaces operating at higher voltage levels. Sofics addresses this challenge through a broad family of I/O topologies co-designed with integrated ESD protection, eliminating the need for external voltage translation components while optimizing power, performance, and area (PPA).

Key Highlights & Topologies:

• Specialty Interface Voltage Support: Enables 1.8V and 3.3V interface capabilities on TSMC’s advanced process nodes, including implementations on TSMC N4C (3.3V) and N2P (1.8V) technologies.
• 4nm 3.3V GPIO Solution: Features integrated voltage regulators allowing reliable 3.3V interfacing directly from core supplies.
• Integrated ESD Co-Design: Built-in ESD protection reduces overall cell area, leakage, and parasitics compared to standard I/O and external protection combinations.
• Customization-Ready Base Architecture: The specialty I/Os are configurable such that they allow rapid tuning of drive strength, slew rate, and power consumption to match specific customer requirements.

“Advanced SoC designs require reliable communication with real-world, higher-voltage system components without sacrificing silicon area or power,” said Bart Keppens, Chief Business Development Officer at Sofics. “By co-designing specialty I/O topologies with optimized ESD protection, we enable IC designers to achieve their target voltage tolerances on TSMC’s advanced nodes quickly and reliably.”

Sofics has been a member of the TSMC Open Innovation Platform® (OIP) IP Alliance since 2010. Many fabless companies have successfully integrated Sofics IP into their designs on TSMC process nodes spanning from mature planar technologies through to FinFET processes.

Explore Sofics IP:

• TSMC 2nm 1V2 GPIO
• SMC 2nm 1V8 ESD Power Clamp – Low Leakage
• TSMC 2nm 1V8 ESD Local Clamp – Low Leakage

Availability 

The specialty I/O topologies and associated IP blocks are validated and available for licensing. Other variants can be derived using Sofics’ internal design flow. Contact us for datasheets.

About Sofics

Sofics (www.sofics.com) is a semiconductor IP provider that has supported fabless companies worldwide with specialty I/Os and on-chip ESD protection. Sofics IP is integrated in IC designs across mature, mainstream and advanced processes.