Rambus invests $5 million in NurLogic, sees synergy in business models
Rambus invests $5 million in NurLogic
By Semiconductor Business News
January 22, 2001 (4:06 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010122S0043
SAN DIEGO -- NurLogic Design Inc. here today announced $5 million in funding from Rambus Inc., which is helping the four-year-old company to finance development of new communications and connectivity chip technologies. Privately-held NurLogic supplies high-speed chip technologies for broadband CMOS and silicon-germanium (SiGe) ICs. Rambus, the developer of wide-bandwidth DRAMs and memory interfaces, sees the investment as a "natural fit given the synergy between the two companies' business models, high-speed I/O technologies, and share vision for future connectivity requirements," said Kevin Donnelly, vice president of the Network Connections Division at Rambus. "As part of the agreement, both companies will work together to ensure NurLogic's future products interface with Rambus' serial link technologies for broader industry deployment," added the Rambus vice president, based in Los Altos, Calif. The $5 million investment marks the first ti me that NurLogic has received funding from another company in the past four years. According to company officials, NurLogic is profitable. "NurLogic has been seeking a strategic investor in order to more fully exploit today's explosive growth in the connectivity and communications markets," said Dave Matty, president and CEO of the San Diego company. "Rambus is an ideal partner for us in that they offer the potential for product collaboration based on a shared vision for high-speed connectivity. NurLogic will also benefit from the experience of Rambus' successful pioneering work in the IP industry." In addition to licensing its Rambus DRAM architecture, Rambus has begun collecting additional royalties for its patents in high-speed synchronous DRAM interfaces, and it is involved in lawsuits with Infineon, Micron, and Hyundai.
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related News
- Rambus Initiates $100 Million Accelerated Share Repurchase Program
- Chips&Media Signs $5 Million IP License Agreement, Marking First NPU IP Contract
- SEALSQ and Quobly sign $5 Million commercial agreement to integrate post-quantum security into next-generation silicon quantum computing platforms
- New NurLogic, Get2Chip Program Targets System-On-Chip Designers
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options