Jennic proposes test bus for IP cores

Jennic proposes test bus for IP cores
By Chris Edwards, EE Times
October 23, 2000 (8:47 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001023S0078

LONDON — Jennic Ltd. (Sheffield, England) has developed a way of adding test access to intellectual property (IP) cores that makes it possible to isolate them for individual tests and let them interact with other cores for system-level tests when they are assembled into a system-chip design.

The overall approach behind Jennic's Scanbus is similar to that taken by the IEEE1149.1 JTAG bus. The intention is to reduce the number of test vectors that would ordinarily be needed if automatic test-pattern generation were used on a full-chip design. It also makes it possible to reuse tests that focus on the internal behavior of a particular IP core.

Scanbus is implemented as a wrapper for each core along with a controller to handle each of the possible test-access mechanisms. In isolation-mode, typical tests include functional and path-delay at the core level and logic scans.

In interaction mode, tests will include chip-level burn-in, path-delay tests between connected IP cores and power-down control for IDDQ analysis.

Instead of having a single scan chain, the company has defined a system that allows up to 32 to be deployed on-chip. Each IP core can be accessed by more than one of those scan chains so that, as well as testing cores in parallel, different functions within large cores can also be exercised simultaneously.

The Scanbus is typically driven using an external port that is up to 32 bits wide.

Chris Edwards is editor of Electronics Times, EE Times' sister paper in the U.K.