IP Cores, Inc. Releases LZR4D Terabit-Class Ultralow-Latency Single-Engine LZ4 Decompressor Core

Palo Alto, California – July 28th, 2026 – IP Cores, Inc. announces the release of the new LZR4D single-engine ultralow-latency lossless decompression core for the LZ4 format, delivering 256 bits of decompressed data per clock with less than 30 clock cycles of latency.

"The LZR4D core represents a significant step forward in hardware decompression performance," said Dmitri Varsanofiev, CTO of IP Cores, Inc. "A single LZR4D engine sustains 256 bits of output per clock, a multiple of the throughput of decompressor cores currently available on the market, without resorting to arrays of parallel engines and the block-level stream splitting they require. Combined with a latency of under 30 clock cycles, the core adds only 10 to 20 nanoseconds of decompression delay in advanced semiconductor nodes, making on-the-fly decompression practical in the data path of storage controllers, memory subsystems, and network processors."

Explore IP Cores IP:

• 256 bit per clock LZ4 Decompressor Core