IC Nexus to begin HSIO (High Speed I/O) ASIC design with Fujitsu
Taipei, Taiwan, November 24, 2004 --- IC Nexus Ltd. today announced the start of a HSIO ASIC project with a well-known global semiconductor design house. The project contains several HSIO macros including PCI-Express, SATA and other glue logic. It is to be fabricated with Fujitsu's 0.13um process. With well establish support from Fujitsu, IC Nexus will continuously devote its efforts on the service for Giga data rate HSIO ASIC designs inlcuding PCI-Express, SATA2, SGMII, etc...
About IC Nexus
IC Nexus is a key provider for Fujitsu's broad range of ASIC technologies, processes, and IP solutions in Taiwan's hugely competitive silicon industry. The Company credits its success to a strong technological base, a competent and qualified workforce, and a highly trained, strategically distributed support network.
With flexible access to state-of-the-art ASIC manufacturing facilities and with strong ties and tight integration to major assembly and testing partners, IC Nexus is able to provide solutions for the most advanced, cost-effective, and appropriate processes to successfully meet the most demanding of schedules and budgets.
For more information about IC Nexus, visit http://www.icnexus.com
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related News
- Cadence Completes Acquisition of Hexagon’s Design and Engineering Business, Advancing Leadership in Physical AI and Multiphysics
- Combined CapEx of Top Eight CSPs to Exceed $710 Billion in 2026; Google Leads ASIC Deployment with TPUs
- Siemens accelerates integrated circuit design and verification with agentic AI in Questa One
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
Latest News
- GUC Collaborate with Wiwynn to Advance Silicon-to-System Infrastructure for Next-Generation Hyperscale AI
- Two Weebit Nano product customers tape-out; one already demonstrating a functional prototype
- JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap
- Altera Brings Determinism to Physical AI Systems with Latest Release of FPGA AI Suite
- Mosaic SoC raises $3.8M to bring real-time spatial intelligence to every consumer device