IBM, Samsung, Infineon, Chartered describe 65-nm process

Mark LaPedus
(12/14/2004 11:43 AM EST)

  SAN FRANCISCO — At the International Electron Devices Meeting (IEDM) here, Chartered, IBM, Infineon and Samsung are expected to describe a 65-nm process that claims to have a 35 percent performance boost over the previous technology.

In recent times, IBM Corp. has signed separate foundry and technology deals with Advanced Micro Devices Inc., Chartered Semiconductor Manufacturing Pte. Ltd., Infineon Technologies AG and Samsung Electronics Co. Ltd.

IBM, the lead technology provider in the alliance, has announced its 90-nm process. Now, the company, along with its partners, have apparently rolled out the 65-nm technology.

The 65-nm process, according to the paper at IEDM, includes two platforms: a base and low-power offering. Applications include logic, SRAM, mixed-signal, and embedded memory.

With the technology, the companies claimed to have achieved SRAM cell sizes of 0.51-to-0.68². The process is said to offer up to 10 levels of interconnect and nine levels of copper. The low-k dielectric has been extended from IBM's 90-nm process, which is based on a proprietary carbon-doped oxide material and deposited via CVD tools from Applied Materials Inc.

A 12.5 angstrom plasma nitrided gate oxide is also deployed. The technology covers a wide range of off-state leakage currents from 0.5- to 50-nA, according to the paper.

"Moreover, we offer an additional low leakage flavor in this technology with low power devices, with gate leakage less than 30 pA/micron and GDIL lower than 10 pA/micron.