Get2Chip synthesis linked to Verplex formal tool

Get2Chip synthesis linked to Verplex formal tool
By Michael Santarini, EEdesign
November 6, 2001 (4:47 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011106S0059

SAN MATEO, Calif. — The tools of ASIC synthesis startup Get2Chip Inc. and formal verification vendor Verplex Systems Inc. have been linked under a partnership between the two companies.

The companies said they have established a "seamless" flow between Get2Chip's Volare synthesis tool and Verplex's Conformal logic equivalence checker.

Get2Chip and Verplex are working to head off tool interoperability problems.

The net result, the companies said, ensures that Conformal can directly process Verilog RTL generated from Volare's high-level synthesis, a user's hand-coded Verilog, and the gate-level netlist produced by Volare.

Users can enter the joint flow at the architectural, RTL or gate levels and do equivalence checks between the gate-level netlist at any given step back to the original RTL, as well as RTL-to-RTL and gate-to-gate.