ESL needs more work, panelists say
Richard Goering, EE Times
(02/09/2006 2:11 PM EST)
SANTA CLARA, Calif. — Electronic system level (ESL) design tools and methodologies have value, but many capabilities have yet to be developed, according to users and vendor representatives at a panel at the DesignCon 2006 conference here Wednesday (Feb. 8).
The panel was entitled "The bottom-line business impact of ESL: getting the right architecture right." Moderator Daya Nadamuni, analyst at Gartner Dataquest, described three ESL design methodologies identified by Dataquest — algorithmic, processor/memory, and control logic.
Jack Donovan, co-founder of training firm ESLX, said that customers are looking for requirements traceability, early software development, reuse of verification models, and behavioral synthesis.
(02/09/2006 2:11 PM EST)
SANTA CLARA, Calif. — Electronic system level (ESL) design tools and methodologies have value, but many capabilities have yet to be developed, according to users and vendor representatives at a panel at the DesignCon 2006 conference here Wednesday (Feb. 8).
The panel was entitled "The bottom-line business impact of ESL: getting the right architecture right." Moderator Daya Nadamuni, analyst at Gartner Dataquest, described three ESL design methodologies identified by Dataquest — algorithmic, processor/memory, and control logic.
Jack Donovan, co-founder of training firm ESLX, said that customers are looking for requirements traceability, early software development, reuse of verification models, and behavioral synthesis.
To read the full article, click here
Related Semiconductor IP
- ONFI/Toggle IP
- 8 - 24MHz Xtal Oscillator on TSMC 22nm
- 32kHz Xtal Oscillator on TSMC 22nm
- 1.056GHz SSCG PLL on TSMC 40nm
- 1.25GHz Multiplying PLL on TSMC 40nm
Related News
- ESL may rescue EDA, analysts say
- Platform ASICs a natural fit at 90 nm, say DAC panelists
- Software limits multi-core ICs, panelists say
- Startups say ESL adoption accelerating
Latest News
- SiFive Paves the Path to Accelerated Adoption of RISC-V in the Datacenter with the BigSky Development Server
- Perceptia Releases Design Kit for pPLL03 on Samsung Foundry 14LPU Platform
- Brite Semiconductor Releases 28nm High-Performance SAR ADC IP, Driving Upgrades for High-Speed Signal Chain Applications
- Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure
- BrainChip Launches Symphony Community Akida Bundle For IBM’s Workload Management Solution