EE Slashes CPU Design Cost
4.5B transistor tapeout for less than $1M
Rick Merritt, EETimes
10/5/2016 00:01 AM EDT
SAN JOSE, Calif. — One engineer, with a little help from contractors, taped out in less than a year a 4.5 billion transistor chip that on paper kicks out more GFlops/mm2 than Intel’s top-end processors. Andreas Olofsson says the Adapteva Epiphany-V shows a hundred-fold efficiency gain in the way chips can be designed.
Some of Olofsson’s gains come from the fact the research chip employs a single core replicated 1,024 times and much of the IP is an evolution from prior designs. Nevertheless, the chip used a state-of-the art 16FF+ TSMC process and fits into a compact 117mm2.
To read the full article, click here
Related Semiconductor IP
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
Related News
- Lattice Slashes Cost, Speeds Development of Mobile Devices With New Plug-In-&-Go USB iCEstick FPGA Evaluation Kit
- Synopsys Supports New Arm AGI CPU with Full-Stack Design Solutions
- Tenstorrent Productizes RISC-V CPU And AI IP
- Kerala Positions Design and IP at Core of Chip Strategy
Latest News
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- Vayavya Labs and Tenstorrent Partner to Accelerate RISC-V Hardware and Software Development Through Virtual Platform Modeling
- RaiderChip’s Edge NPU reaches more than 50 Generative AI Models with the addition of Qwen3.8-27B