Cortus Launches High Performance Dual-Issue IP Core for Embedded Applications

New APS core from Cortus delivers high performance for embedded System-on-Chip applications

Montpellier, France. 11th October 2016 - Cortus, a technology leader in low power, silicon efficient, 32-bit processor IP, announced the release of the APS29 - a high performance, dual issue version of its APS25 IP core today. This is the fourth in a family of products based on the Cortus v2 instruction set. The core is aimed at embedded systems requiring good computational performance while also delivering efficient silicon area and modest power dissipation.

“For companies developing embedded systems with demanding computational requirements, our ASP29 core offers outstanding performance while efficiently using silicon area”, says Michael Chapman President & CEO of Cortus. “It is the first of a number of Cortus cores offering greater computational performance”.

The APS29 has a Harvard architecture, sixteen 32-bit registers, a 64-bit accumulator and a 5-7 stage pipeline. The APS29 has two execution units, enabling it to execute up to two instructions at once, the two units are similar and both access the register set. The only difference is that one of the two ALUs features a multiply-accumulate unit, while the other has the simpler multiplier. The processor automatically dispatches the multiply-accumulate instructions to the appropriate execution unit; it also has a branch predictor and a load/store unit which will coalesce adjacent 32 bit operations into a single 64 bit operation. The core delivers 3.09 DMIPS/MHz and 3.63 CoreMarks/MHz*. This is about 47% more than the comparable single issue APS25.

APS29 supports 64-bit AXI4™ busses enabling two 32-bit reads or two 32-bit writes to be undertaken simultaneously with a 64 bit fetch for instructions. Using a 28 nm technology the CPU area starts at around 0.037 mm2 (optimised for area) and when optimised for speed can achieve 1,400 MHz. Up to eight co-processors can be added to an APS29 core. The Cortus coprocessor interface allows licensees to add custom coprocessors, for example to accelerate computations in cryptography or signal processing, without knowing details of the internals of the core. Co-processor instructions can be inserted into C-code appearing as function calls.

All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS™, Micrium μC/OSII®, Micrium μC/OSIII® & TargetOS™.

To date over 1.2 billion devices have been manufactured containing Cortus processor cores.

About Cortus S.A.S.:
Cortus S.A.S. is a technology enabler for rapidly growing applications including Internet of Things (IoT), wearable electronic devices, smart sensors and security. It has specialised in 32-bit processor cores which can significantly reduce manufacturing costs while achieving good computational performance and meeting tight power constraints. Integrated circuits containing Cortus cores have been manufactured in high volumes for a wide range of applications including automotive, CMOS imaging, M2M controllers, secure execution, sensors, SIM cards, PayTV cards, smart metering and wireless. Cortus’ headquarters are in Montpellier, France.