Asiczen Releases its CAN Verification IP
October 4, 2016 -- Asiczen Technologies announces the release of its UVM based CAN verification IP. azCAN is fully compliant with CAN specification 2.0. azCAN is a UVM based verification component (UVC) that can be used by IP and SOC makers to test their CAN interface design effectively and quickly.
This easy-to-use UVC can be easily integrated to any UVM based environment and can be used to generate a variety of scenario without much effort. CAN is a multi-master serial bus standard for connecting Electronic Control Units [ECUs] also known as nodes. Two or more nodes are required on the CAN network to communicate.
The complexity of the node can range from a simple I/O device up to an embedded computer with a CAN interface and sophisticated software. The node may also be a gateway allowing a standard computer to communicate over a USB or Ethernet port to the devices on a CAN network.

Related Semiconductor IP
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
Related News
- Arasan acheives the Industry's First ASIL-D Certification for its CAN XL IP Core
- ChipAgents Helps eMemory Cut NVM IP Functional-Model Verification Effort by 80%
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- MoSys' 1T-SRAM-Q Technology Verified on UMC'S 0.13-Micron Logic Process; Foundry's Customers Can Now Access MoSys' Newest High-Density Embedded Memory Technology
Latest News
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- Vayavya Labs and Tenstorrent Partner to Accelerate RISC-V Hardware and Software Development Through Virtual Platform Modeling
- RaiderChip’s Edge NPU reaches more than 50 Generative AI Models with the addition of Qwen3.8-27B