ARM adds memory to synthesizable core <FONT SIZE=-1>(by Peter Clarke - EE-TIMES)</FONT>

IP News

ARM adds memory to synthesizable core

By Peter Clarke, EE-Times

PALO ALTO, Calif. — ARM Ltd. (Cambridge, England) unveiled two versions of the ARM9E Thumb processor core with configurable memory subsytems at the Hot Chips conference this week, and announced that LSI Logic Corp. (Milpitas, Calif.) has become the first semiconductor maker to license the designs.

Both the ARM946E and ARM966E cores will be initially available as synthesizable implementations.

The ARM946E macrocell, which combines an ARM9E core with cache, write buffer and a memory protection unit, is aimed at embedded applications running a real-time operating system; the cache architecture enables designers to scale their cache size based on application requirements.

The ARM966E macrocell combines an ARM9E core with a write buffer and SRAM memory, and targets "hard real-time" applications where high performance and low-power consumption are required without the use of caches. Both macrocells feature the AMBA (Advanced Microcontroller Bus Architecture) AHB (AMBA Hi-speed Bus) interface.

Introduced in May 1999 at the Embedded Processor Forum, the ARM9E is a single control and digital signal processing (DSP) core targeted at applications in mass storage, next-generation digital cellular phones, networking, Internet appliances, and automotive and industrial control systems.

The ARM9E core's performance is rated at 220 MIPS at 200 MHz; it sustains one 16x16 or 16x32 multiply-accumulate operation per cycle. Initial 0.25- micron implementations will achieve 160 MHz; future 0.18-micron implementations will achieve 200 MHz and higher.

"ARM developed this new family of DSP-enhanced processor cores to meet the full range of application requirements and cost points," said Carlos Jimenez, CPU product manager at ARM. "The ARM946E and ARM966E cores leverage the numerous benefits of the ARM architecture, and enable our partners to use their existing design flows, cell libraries and test methodologies to reduce development effort and time-to-market."

LSI Logic will include the ARM946E and ARM966E macrocells in the company's synthesis-based CoreWare ASIC design flow.

"We are very pleased with the fully synthesizable features of the ARM9E family which make these cores the perfect addition to LSI Logic's extensive ASIC CoreWare library," said Bob Van Steenburgh, director of processor core marketing at LSI Logic.
 

Previous Page