Tale of Twin Metrics: What To Look For When Buying a Verification IP
November 13, 2014
So what do you value in a verification IP? Most people would say two things – reduction in verification execution effort and zero set up time. While execution effort is reduced by "Completeness" of a VIP, the set up time is reduced by making it more "Customizable".
Having said that, in most VIP development projects, one metric gets compromised at the alter of the other. Often times, while making the Verification IP more complete or “Out of the Box”, VIP developers ignore design choices that would lead to easier/faster customization during set up and execution.
In this blog, we take a closer look at these twin metrics. What do they mean? How does one achieve them? Is there a trade-off between the two?
Related Semiconductor IP
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
Related Blogs
- Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs
- World IP Day: A Time to Reflect on the Value of Semiconductor IP
- Rambus CXL IP: A Journey from Spec to Compliance
- Rambus CXL IP: A Journey from Spec to Compliance
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects