UVM Sequences Tutorial
May 12, 2015
To verify an RTL design, you must define a stimulus (i.e. what kind of data should be sent to the DUT).
In any test-bench environment, the driver is responsible for signal activities at the bit level. SystemVerilog in functional verification provide this abstraction. It introduces the concept of TRANSACTION, GENERATOR and CHANNEL. Transaction is the actual data item which is generated by the Generator. It is sent to the driver through the Channel to drive it on the DUT interface.
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Blogs
- Reusable Sequences in UVM
- Virtual Sequences in UVM: Why, How?
- Functional Verification Basics: UVM Tutorial
- Avoiding Redundant Simulation Cycles for your UVM VIP with a Simple Save-Restore Strategy
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions