Virtual Sequences in UVM: Why, How?
In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively?
Most UVM testbenches are composed of reusable verification components unless we are working on block-level verification of a simple protocol like MIPI-CSI. Consider a scenario of verifying a simple protocol; In this case, we can live with just one sequencer sending the stimulus to the driver. The top-level test will use this sequencer to process the sequences (as described in the previous blog post). Here we may not need a virtual sequence (or a virtual sequencer).
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Related Semiconductor IP
- Verification IP for MIPI SoundWire
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Related Blogs
- Reusable Sequences in UVM
- UVM Sequences Tutorial
- How Virtual Sensors Streamline Complex System Development
- Why SRAM PUF Technology Is the Bedrock of Dependable Security in Any Chip