Functional Verification Basics: UVM Tutorial
May 7, 2015
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which was widely accepted by verification enginees across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
- Separation of tests from test bench
- Transaction-level communication (TLM)
- Sequences
- Factory and configuration
- Message reporting
- End-of-test mechanism
- Register layer
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Basics of Functional Verification
- Functional Verification Basics: What's The Objective of End of Test?
- UVM Sequences Tutorial
- Hardware security verification must go beyond functional testing
Latest Blogs
- How Cache Coherency Simplifies AI Software
- Multiple neuromorphic chips, one grid, no new middleware
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects