Functional Verification Basics: UVM Tutorial
May 7, 2015
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which was widely accepted by verification enginees across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
- Separation of tests from test bench
- Transaction-level communication (TLM)
- Sequences
- Factory and configuration
- Message reporting
- End-of-test mechanism
- Register layer
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related Blogs
- Basics of Functional Verification
- Functional Verification Basics: What's The Objective of End of Test?
- UVM Sequences Tutorial
- Functional verification concepts have to change
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