Understanding Embedded USB2 (eUSB2) and its usage
The need for higher processing power and lower power consumption are driving processors and System on Chip (SoC) to more advanced lower process nodes. For SoCs operating at 1.2V supply that are suitable for mobile phones, tablets, and laptops, using USB2 interfaces is a challenge as it becomes difficult to support 3.3V IO cells. A low voltage USB2.0 solution is therefore required to address the gap.
The embedded USB2 (eUSB2) Physical Layer Supplement to the USB 2.0 Specification was created to address the need for a low voltage, power-efficient USB 2.0 PHY solution. It eliminates the need for 3.3V IO signaling in small process technologies.
To read the full article, click here
Related Semiconductor IP
- eUSB2 PHY
- eUSB2 Repeater
- eUSB2 v1.1 Dual-Role, repeater/native mode PHY, SamSung 28FDSOI, 1.8V, N/S orientation
- eUSB2 v1.1 Dual-Role, repeater/native mode PHY, SamSung 3LPE, 1.2V, N/S orientation
- eUSB2 v1.2 Dual-Role, repeater/native mode PHY, SamSung SF3P, 1.0V, N/S orientation
Related Blogs
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- Embedded World 2023: it's time to architect all ambitions with custom compute
- Understanding USB IP and Its Role in SOC Integration
Latest Blogs
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution