UCIe Interoperability Between Intel and Cadence

By Cadence

November 9, 2023

Intel and Cadence are collaborating on an initiative to demonstrate interoperability between Intel’s UCIe IP and Cadence’s UCIe IP.

UCIe is the latest emerging open specification defining the interconnect between two die links in a system in package (SiP). UCIe is expected to enable power-efficient and low-latency chiplet solutions as heterogeneous disaggregation of SoCs becomes mainstream to overcome the challenges of Moore’s Law. The UCIe 1.0 standard, dated February 24, 2022, first became available in March 2022. A newly updated UCIe 1.1 specification was recently released and announced on August 8, 2023.

Emerging new standards often present unique challenges and limited opportunities for interoperability. Intel and Cadence have collaborated on simulation interop initiatives for a number of years and previously demonstrated CXL and PCIe-IDE interoperability as these new standards emerged. Intel and Cadence are now working together to demonstrate UCIe interoperability of Intel’s UCIe IP and Cadence’s latest UCIe IP solutions. The first step towards this collaboration is a demonstration of pre-silicon RTL co-simulation interoperability.

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