Viewpoint: Towards a lean and mean SystemVerilog
IEEE Std. 1800-2009 – A Merger of Two Titans
IEEE Std. 1800-2009 combines Verilog and SystemVerilog (SV) languages under the auspices of one single language standard. This was long overdue as the first step towards streamlining what was essentially the same language covered by two different language standards – IEEE Std. 1800-2005 and IEEE Std. 1364-2005.
However, the current version of the standard just starts that process of streamlining and the process is far from being over. This is apparent if one looks at the size of the current standard (1285 pages) and compares it with language standards from other fields, such as ANSI C (C99 has 554 pages) and ECMA JavaScript (ECMA-262 has 258 pages).
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