Viewpoint: Towards a lean and mean SystemVerilog
IEEE Std. 1800-2009 – A Merger of Two Titans
IEEE Std. 1800-2009 combines Verilog and SystemVerilog (SV) languages under the auspices of one single language standard. This was long overdue as the first step towards streamlining what was essentially the same language covered by two different language standards – IEEE Std. 1800-2005 and IEEE Std. 1364-2005.
However, the current version of the standard just starts that process of streamlining and the process is far from being over. This is apparent if one looks at the size of the current standard (1285 pages) and compares it with language standards from other fields, such as ANSI C (C99 has 554 pages) and ECMA JavaScript (ECMA-262 has 258 pages).
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Blogs
- RISC-V and GPU Synergy in Practice: A Path Towards High-Performance SoCs from SpacemiT K3
- LPDDR6: A New Standard and Memory Choice for AI Data Center Applications
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring
- Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification
Latest Blogs
- From Bug Hunting to Engineering Methodology: Lessons from AI-Driven Development
- Manufacturing Intelligence: Turning EDA Data into Trusted Action
- Execute-in-Place: Getting More from Embedded NVM
- Rethinking RTL flows with AI-driven hybrid formal verification
- Arm and NVIDIA: Building the trusted compute foundation for the agentic AI era