The best laid plans of mice and men
Last month on these pages I discussed "The elephant in the corner"–the wholly unrealistic IC development schedule nobody dares openly question. In truth, the situation is often much worse than I described. Usually it isn't just one elephant in the corner, there's a herd—a portfolio of projects. In fact, one of the most insidious problems of portfolio management is the failure to adequately verify that project plans are realistic. Because most R&D organizations lack a reliable verification capability, most portfolios end up in chaos—indeed, "the best laid (portfolio) plans of mice and men often go awry."
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- Pasteur’s Magic Quadrant in AI: The Fusion of Fundamental Research and Practical
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
- The Silent Guardian of AI Compute - PUFrt Unifies Hardware Security and Memory Repair to Build the Trust Foundation for AI Factories
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing