Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification
June 20, 2013
I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A recent article described Fujitsu Semiconductor's experience -- 35% better performance, 35% smaller area, 51% less power and faster turnaround time.
The benefits of moving up in abstraction are summarized by the following graph, which shows the leaps in productivity for every leap in abstraction:
To read the full article, click here
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Blogs
- Design, Verification, and Software Development Decisions Require a Single Source of Truth
- Importance Of Hardware Security Verification In Pre-Silicon Design
- IDS-Verify™: From Specification to Sign-Off – Automated CSR, Hardware Software Interface and CPU-Peripheral Interface Verification
- AI in Design Verification: Where It Works and Where It Doesn’t
Latest Blogs
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA
- Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments