System in Package, Why Now?

By Cadence

December 9, 2019

At HOT CHIPS this summer, one of the things I noticed was just how many of the designs being presented were in some form of 3D packaging with multiple die. I wrote about many of them in my post HOT CHIPS: Chipletifying Designs. At last year's HOT CHIPS, I don't remember any designs being presented like this. So that raises the obvious question, why now?

Moore and More

For over 50 years, the semiconductor industry has enjoyed the benefits of Moore's Law. But now the economics of semiconductor scaling are over. Moore's Law was mainly an economic law. If you read his original article (based on four datapoints!), he points out that the economically optimal number of transistors on a chip was doubling every couple of years. Of course, underlying it was the development of technology to make this be true, and until a few years ago that continued. The very high-level economic proposition was that each process generation doubled the number of transistors in the same area, at a cost increase of just 15%, leaving a cost saving of 35% per transistor. But now transistors are more expensive each generation, since the processes are so complex and the capital investment to build a working fab (these days, including EUV steppers at over $100M each). So we have a process roadmap from 7nm, to 5nm, to 3nm, and a couple of generations after that. But the economics are such that these processes will not just be more expensive per wafer, as has been true for decades, but more expensive per transistor.

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