Source of IP: Silicon foundries provides 18% of Design IP blocks, IP vendors only 16% to Fabless
Thanks to the Semiconductor Ecosystem Survey from GSA-Wharton and the key indicators of semiconductor companies’ technology strategies related to IP:
- IP Reuse: On average, a fabless semiconductor company reuses about 63% of design IP in the revision of an existing product design and about 44% in a new product design.
- Source of IP: Silicon foundries are becoming an important source of design IP for fabless companies in addition to third-party IP firms. On average, 18% of design IP blocks are from the foundry's portfolio/library, followed by 16% for third-party licensing firms.
The other key indicators are about differentiation and time-to-market. Let’s make some comments. First of all, as I am focusing on IP… I am happy, as the report clearly links IP as one of the major source of innovation. But, when I think to my blogger colleagues who’s focus is on EDA (namely, Dan Nenni, Daniel Payne and Paul McLellan), I think they have good reasons to be disappointed, as within the 26 pages you will never found the mention of EDA. The report is dealing about “Innovation”, “partners” and “ecosystem”, referring to the fables companies, so –intentionally or not- deciding to omit EDA companies in the ecosystem looks strange to me… Let’s come back to IP. The number of design IP blocks coming from foundries (18%) is higher than these coming from the IP vendors (16%). Is it a surprise? No, as when looking at the list of IP offered by the major foundries, you realize that this list is pretty long, even if we can qualify these IP as commodities in most of the cases. Yes if you consider the large number of IP vendors (more than 460 listed on D&R).
To read the full article, click here
Related Semiconductor IP
- 1.6T Ultra Ethernet Controller
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
Related Blogs
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- Trillions of Cycles per Day: How SiFive Boosts IP and Software Validation with Synopsys HAPS Prototyping System
- Rambus RT-660 Root of Trust IP Achieves FIPS 140-3 Certification
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP