Semico's SoC hierarchy. What do you do with a platypus SoC?
February 11, 2011
For the past couple of weeks, I’ve been writing about several aspects of Semico’s IP Subsystem report. (see “Are IP subsystems the next big IP category?”) The report’s premise is that the rise of IP Subsystems—IP blocks that deliver complete functions such as video or audio through a collection of design IP, software stacks, application software, and verification IP—fundamentally change the way SoCs are and will be developed in advanced process nodes. (Note: this is a concept that’s firmly embedded in the EDA360 vision.) A significant factor not yet covered in this blog is how the hierarchy of SoC definitions and metrics changes with this step up in IP complexity. This blog entry rectifies that omission.
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
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- Real Number Model Development and Application in Mixed-Signal SoC Verification
- Want to see the future of low-power SoC design? Have a look into Gary Smith’s crystal ball
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