Semico's SoC hierarchy. What do you do with a platypus SoC?
February 11, 2011
For the past couple of weeks, I’ve been writing about several aspects of Semico’s IP Subsystem report. (see “Are IP subsystems the next big IP category?”) The report’s premise is that the rise of IP Subsystems—IP blocks that deliver complete functions such as video or audio through a collection of design IP, software stacks, application software, and verification IP—fundamentally change the way SoCs are and will be developed in advanced process nodes. (Note: this is a concept that’s firmly embedded in the EDA360 vision.) A significant factor not yet covered in this blog is how the hierarchy of SoC definitions and metrics changes with this step up in IP complexity. This blog entry rectifies that omission.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Hand-crafted for horsepower: Apple A6 SoC
- Altera's Real Impact with ARM based SOC FPGAs
- How much SRAM proportion could be integrated in SoC at 20 nm and below?
- On-chip networks: Future of SoC design
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing