Risk Avoidance, Hardware Emulation Style
Risk aversion, which comes from the uncertainty associated with committing a design to silicon, is the name of the game.
December is normally a month in which we take a moment to look back over the preceeding year. With this in mind, I skimmed through the blog posts I've written for EE Times in 2015 on one of my favorite topics -- hardware emulation. What struck me as an unwritten, but recurring, theme is hardware emulation's ability to alleviate risk for development teams and project managers.
I can think of an analogy to buying an insurance policy. Such a policy may protect you and your family against the risk of a premature death, a house disaster, a car crash, and other unforeseen calamitous events. Likewise, hardware emulation provides insurance to reduce, or eliminate, costly re-spins. And, even more important, hardware emulation can accelerate time-to-market by delivering thoroughly verified RTL and gate-level designs to the backend design flow, along with validated embedded software ahead of silicon availability. Furthermore, it can perform post-silicon testing to weed out any bugs remaining after tape-out.
"Why and how is all this possible?" you may wonder.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Blogs
- The Future of Hardware Emulation
- A Great Match: SoC Verification & Hardware Emulation
- Hardware Emulation: One Verification Tool, Unending Possibilities
- Today's Complex Networking Chips Demand Hardware Emulation
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP