Risk Avoidance, Hardware Emulation Style

By EETimes

December 17, 2015

Risk aversion, which comes from the uncertainty associated with committing a design to silicon, is the name of the game.

December is normally a month in which we take a moment to look back over the preceeding year. With this in mind, I skimmed through the blog posts I've written for EE Times in 2015 on one of my favorite topics -- hardware emulation. What struck me as an unwritten, but recurring, theme is hardware emulation's ability to alleviate risk for development teams and project managers.

I can think of an analogy to buying an insurance policy. Such a policy may protect you and your family against the risk of a premature death, a house disaster, a car crash, and other unforeseen calamitous events. Likewise, hardware emulation provides insurance to reduce, or eliminate, costly re-spins. And, even more important, hardware emulation can accelerate time-to-market by delivering thoroughly verified RTL and gate-level designs to the backend design flow, along with validated embedded software ahead of silicon availability. Furthermore, it can perform post-silicon testing to weed out any bugs remaining after tape-out.

"Why and how is all this possible?" you may wonder.

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