RISC-V - Instruction Sets Want to Be Free

By _Cadence - Breakfast Bytes

June 27, 2016

I had never heard of RISC-V (pronounced five, not vee) until earlier this year when there was a presentation about it at EDPS in Monterey. I immediately texted the daughter of a friend of mine who is a CS major at Berkeley where it originated and she gave me a bit more background. Then, at DAC last week, Krste Asanovic, one of her professors, gave a SkyTalk on the topic. It was the only pavilion presentation I went to during DAC where every seat was filled and there were lots of what MUNI here in San Francisco calls "standees" (wouldn't they be people being stood on?).

Instruction set architectures (ISAs) matter. As he pointed out, it is one reason that Intel struggles to get a foothold in mobile. Or that ARM struggles in servers. As Krste pointed out, the main instruction set in all those datacenters is officially the AMD 64-bit x86 ISA, even though most of the processors are built by Intel. When the 32-bit to 64-bit transition happened, Intel tried to move everyone to its new instruction set (jointly developed with HP) called Itanium, but people preferred to stick with an x86-compatible architecture. When AMD got traction, Intel had to compete aggressively and eventually Itanium was left to die a slow death. ISAs are also where the software meets the hardware, so they are one of the key interfaces in any system.

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