INTERA Neuromorphic SDK: From Spiking Neural Networks to RISC-V Hardware

By INTERA Group

October 27, 2026

From Spiking Neural Networks to RISC-V Hardware in Minutes

The INTERA Neuromorphic SDK transforms trained Spiking Neural Networks (SNNs) into deployable and measurable embedded applications, providing developers with an end-to-end workflow from AI model training to hardware execution.

Models trained using SNNTorch, Lava-DL, or other NIR-compatible frameworks can be exported to the open Neuromorphic Intermediate Representation (NIR) format.

The SDK then quantizes the network, compiles it using an MLIR-based compiler, maps supported operations onto INTERA's neuromorphic accelerators, generates firmware, and deploys the application to a RISC-V FPGA platform.

Throughout this process, developers can evaluate essential performance metrics, including model accuracy, inference latency, and memory usage.

Unlike runtime interpretation approaches, the SDK relies on compiler-generated code, reducing the need for manually written firmware and simplifying the transition from research models to embedded hardware.

Its open-source foundation supports interoperability and reduces dependence on proprietary model formats.

From AI Model to Embedded Hardware

The INTERA Neuromorphic SDK provides an integrated development workflow that connects neural network training, model representation, compilation, and hardware execution.

End-to-end workflow:

SNNTorch / Lava-DL → NIR → MLIR → RISC-V / FPGA

This approach enables developers to move from SNN experimentation to embedded deployment through a reproducible process, while reducing the complexity traditionally associated with neuromorphic hardware development.

Hardware Acceleration Support

The SDK is designed to support three execution targets on the same development board, enabling developers to compare performance across CPU-based and hardware-accelerated implementations.

RISC-V CPU: Reference Execution

The complete neural network runs on the host RISC-V CPU, providing a baseline for validating model behaviour and measuring acceleration benefits.

EAGLE: Near-Memory Acceleration

EAGLE accelerates synaptic matrix-vector operations using its near-memory architecture, while neuron dynamics remain on the CPU.

This configuration allows developers to evaluate the benefits of hardware-accelerated neural computation while retaining software control over neuron processing.

EAGLE Spiking: Full-Layer Hardware Acceleration

EAGLE Spiking is designed to execute complete SNN layers in hardware, including synaptic operations, bias calculations, neuron dynamics, and spike generation.

Neuron states remain in accelerator memory across timesteps, reducing unnecessary data movement between processing components.

Together, these execution targets provide developers with a flexible environment for evaluating different neuromorphic processing architectures.

Open Source and Community Standards

INTERA supports the development of neuromorphic computing through open standards and interoperable software technologies.

The Neuromorphic SDK builds on established frameworks and compiler infrastructure, combining an open-source foundation with specialised accelerator backends.

Its key capabilities include:

• NIR-native compatibility: Models from SNNTorch, Lava-DL, and other compatible frameworks can be imported without a proprietary model representation.
• Open-source SNN-MLIR: An MLIR dialect, NIR front end, and CPU lowering infrastructure published under the Apache-2.0 licence with LLVM exception.
• LLVM/MLIR infrastructure: A compiler architecture supporting extensibility, portability, and hardware-specific optimisation.
• INTERA accelerator backends: Specialised compilation support designed to map compatible operations onto neuromorphic acceleration hardware.

The open-source SNN-MLIR project is available through GitHub and PyPI, with its architecture documented in the research paper SNN-MLIR: An MLIR Dialect for Compiling Neuromorphic SNNs from NIR to Bare-Metal C.

Explore INTERA's SNN-MLIR project on GitHub

Why the INTERA Neuromorphic SDK Matters

Deploying Spiking Neural Networks on embedded hardware traditionally requires developers to navigate several complex processes.

These challenges include framework-specific model formats, manual quantization, custom firmware development, FPGA deployment workflows, and fragmented benchmarking tools.

The INTERA Neuromorphic SDK addresses these challenges through an integrated development environment that offers:

• Standards-based model interoperability through NIR.
• Automated integer quantization for supported network configurations.
• Compiler-generated embedded code instead of manually implemented inference routines.
• Automated memory layout adapted to the execution target.
• Streamlined deployment workflows for supported RISC-V FPGA configurations.
• Integrated performance evaluation covering accuracy, latency, and memory requirements.

By combining these capabilities, the SDK helps engineering teams simplify neuromorphic development and evaluate hardware acceleration using consistent, reproducible workflows.

Real-World Applications and Development Use Cases

The INTERA Neuromorphic SDK supports several important development scenarios.

Neuromorphic Edge Prototyping

Transform trained SNNTorch models into executable applications on RISC-V hardware through a reproducible compilation workflow.

Hardware Accelerator Evaluation

Compare CPU-based execution with EAGLE and EAGLE Spiking configurations to assess hardware acceleration benefits.

SNN Performance Benchmarking

Evaluate model accuracy, inference latency, and memory requirements across supported execution targets.

Research-to-Hardware Deployment

Move NIR-compatible research models towards deployable embedded applications without manually rewriting the complete inference implementation.

These capabilities help bridge the gap between neuromorphic research and practical embedded AI development.

Train with SNNTorch. Compile with MLIR. Run on Neuromorphic Hardware.

The INTERA Neuromorphic SDK provides engineering teams with an open, standards-based path from Spiking Neural Network research to optimised, deployable applications on RISC-V embedded platforms.

By integrating model interoperability, hardware-aware compilation, neuromorphic acceleration, and performance evaluation, INTERA aims to make advanced SNN development more accessible and practical for next-generation Edge AI applications.

Explore the INTERA Neuromorphic SDK

Interested in exploring a sparse or neuromorphic AI workload?

Contact INTERA to discuss your application, model requirements, development environment, and target hardware platform.

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Email: sales@intera-group.com

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