Rhines Calls For Honesty On Nodes
Wally Rhines, CEO of Mentor Graphics, agreed with Malcolm Penn, CEO of Future Horizons, that the measurements put on process nodes have become fictional.
Rhines told the IEF2013 meeting in Dublin that the progress of Moore’s Law, which transistor cost declined 30% every 18 months, and the dictates of the learning curve which meant that a doubling of the volume reduced the cost by 30%, meant thst process became all-important in the semiconductor business.
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