DRAM vendors look to 40nm process technology to keep DRAM profits flowing next year
Taiwan Economic News reports that DRAM vendors will be bringing 4x nm process technologies on line during 2010 and 2011 to keep manufacturing profits up. According to P L Pai, vice president of Nanya Technology, DRAM chip makers are presently climbing the learning curve with 40nm process technologies and he says that the lead time of 40nm immersion tools averages nine months.
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Blogs
- Blogging from Taiwan: TSMC and 40nm Yield
- TSMC 40nm Yield Explained!
- Moore’s Law and 40nm Yield
- Anticipating the (40nm) Deluge
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions