ARM 1176 in IBM SOI process demonstrates a cell-based flow
For several years it has been clear that SoI processes have a more favorable speed vs. voltage characteristic than comparable-node bulk silicon processes. This advantage can mean either lower operating voltage at a given speed---and thus lower power—or higher performance at a given voltage. And the presence of vast quantities of both the Xbox 360 and the PlayStation-3 should eliminate any question about volume manufacture, at least from IBM. So why is SoI still so rarely used?
The normal answer is the lack of design infrastructure. Early on, most SoI designs were at the high-performance fringe, and so people rightly associated SoI with custom design and highly-skilled teams. It would require new device models, new libraries, and new tools to make SoI work in a normal cell-based RTL flow, this reasoning said.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Blogs
- SOI need a large IP Ecosystem, 100% Reliable Novocell NVM IP is now part of IBM SOI 32nm ecosystem
- Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow
- TSMC vs GlobalFoundries vs IBM
- Bringing MEMS and asynchronous logic into an SoC design flow
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space